This invention pertains to voltage buffers to drive analog voltages, and, in particular, relates voltage buffers for large and potentially variable capacitive loads.
A conventional driving circuit or driver for a capacitive load typically consists of a signal input, a signal output, and an amplifier of an analog voltage buffer to drive the load. A common example of such a circuit is shown in FIG. 1a. A driver of this kind is used when it is wanted to apply a reference voltage, Vin, to a load, but the source of the reference voltage cannot drive the load sufficiently. This particular example uses an amplifier with a source follower output stage. Other examples include using am amplifier with a class A or a class A/B output stage. In all of cases, the output voltage, Vout, is taken of a node in the feedback loop for the op-amp or differential gain stage 11 and, consequently, the load, Cload 31, is part of the feedback loop.
Considering FIG. 1a in move detail, an input voltage Vin is supplied to a buffer including differential gain stage 11 connected between a voltage source and, through current limiter 21, ground, where the transistor 13, here an NMOS, is explicitly shown. The feedback loop to the amplifier 11 is closed from a node between the transistor 13 and the current limiter, from which is also supplied the output voltage, Vout. Consequently, the load to which the output voltage is applied, Cload 31, is part of the feedback loop. (The capacitor Ccomp is discussed below). Instead of the NMOS transistor shown in FIG. 1a for the output transistor 13, variations on this source follower arrangement could also use PMOS, npn, pnp, or MESFET transistors, as is known in the art. For example, a PMOS transistor could be used for output transistor 13, in which case the rest of FIG. 1a would be changed as shown in FIG. 1b, with the current limiter 21 now placed between the voltage source and ground, and with both the output and the feedback loop to the differential gain stage or op-amp 11 coming from nodes above the PMOS but below the current limiter. As already noted, a class A and class A/B output stage could replace the shown source follower setup of either FIG. 1a or 1b. In addition, the circuits can more generally be connected between two arbitrary voltage levels, where the lower of these is taken as ground in the following to simplify the discussion.
FIG. 4 shows a particular example of an application for a driver such as that shown in FIG. 1a or 1b, as well as for those of the present invention as described below. The driver of these figures is particularly useful in a non-volatile memory system, such as an Electrically Erasable Programmable Read Only Memory (EEPROM) or flash memory having a number of storage elements or cells for storing data therein. An example of a storage element in a memory system is shown in FIG. 4. For purposes of clarity, many of the details of storage elements that are widely known and are not relevant to the present invention have been omitted. Storage elements are described in more detail in, for example, U.S. Pat. No. 5,862,080, which is incorporated herein by reference. Referring to FIG. 4, a memory system typically includes a number of storage elements 175, each having one or more Field Effect Transistors (FETs 180) each having one or more control gate or gate 185 and isolated or floating gate 190, which is electrically isolated from source 195 and drain 200 of the FET. Because gate 185 capacitively couples with floating gate 190, storage element 175 appears to the driver as a capacitive load. Because a large number of storage elements in the non-volatile memory system (not shown) are typically programmed simultaneously, and because a large number of the gates 185 in storage element 175 must be switched simultaneously between a programming voltage and a verify voltage to program the storage element, the gates appear to driver 100 as a single, large capacitive load. The voltage, Vout, supplied to the memory storage based on the input voltage, Vin, can be any of the various programming, read/verify, or other voltages supplied to the storage element during operation of the memory from the power or a high-voltage pump (not shown), either on the same chip as the memory array or from another chip in the memory system. Further examples of such systems where such voltage buffer could be used are given in the following U.S. patents and pending applications that are incorporated herein in their entirety by this reference: U.S. Pat. Nos. 5,095,344, 5,172,338, 5,602,987, 5,663,901, 5,430,859, 5,657,332, 5,712,180, 5,890,192, 6,151,248, and 6,426,893 and Ser. No. 09/667,344, filed Sep. 22, 2000, and Ser. No. 09/893,277, filed Jun. 27, 2001.
Although the designs discussed with respect to FIGS. 1a and 1b provide a unity gain buffer for driving an analog voltage, such as the capacitive loads found in a non-volatile memory, they have several shortcomings. For stability, the feedback loop should have a dominant pole. In the arrangement of FIG. 1a or 1b, the are two contributions to the loop: one from the output node of differential gain stage 11, that is connected to the gate of transistor 13, and the other at the node Vout, that is connected to Cload 31. In many applications, such as the EEPROM example shown in FIG. 4, the driven load has a variable value so that there is no clearly dominant pole in the loop. Thus, the sort of prior art design shown in FIG. 1 is prone to oscillations and slow settling times. A standard prior art technique to stabilize the circuit is to introduce the compensating capacitor Ccomp 12 between the output of the differential gain stage 11 and ground, where value of Ccomp is taken large enough to maintain the dominance of the corresponding pole.
Although the compensation capacitor will stabilize the driver circuit, as the load Cload can be quite large in some applications, the value of Ccomp needs to increase proportionally. This results in the circuit responding slowly as Ccomp must be charged. In addition to the long settling time, this also can result in large quiescent currents through the differential gain stage or op-amp 11 in order to charge Ccomp.